WHY SETUP AND HOLD TIMES EXIST? | STA-2 | Static Timing Analysis

Hello,
Welcome to The Rising Edge!
I am Yash and this is the second part of Static Timing Analysis.
In this video, you will learn about the reason for the existence of Setup and Hold Times by understanding the internal structures and working of the D-latch and Flip-Flop with a brief introduction to the transmission gate.
Part 1(Introduction to Setup and Hold Times): • INTRODUCTION TO SETUP ...
Part 3(How the Hold Time can be NEGATIVE): • HOLD TIME CAN BE NEGAT...
Part 4(Setup Analysis and Maximum Clock Frequency): • SETUP ANALYSIS | MAXIM...
Part 5 (Hod Analysis): • HOLD ANALYSIS | STA - ...
Part 6 (STA Interview Problem): • STA INTERVIEW QUESTION...
Complete STA Playlist: • Static Timing Analysis
Stay tuned for the complete series, keep learning, and All the Best for your placement preparation.
#STA #Setup #Hold #StaticTimingAnalysis #SetupViolation #HoldViolation #SetupAndHoldTimes #FlipFlop #DigitalElectronics #PlacementPreparation
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Video Link: • Ikson - Spring (Vlog N...

[@anjaliagrawal4269]

Your concepts are very clear and your attempt to make them understandable for others is praiseworthy. Good work👌

[@RISHABHSINGH-uk3tm]

Aapne engineering Safal Kardi humaari ..Samajh aa gya ache se sir

[@therisingedge]

This is my only goal. To help you guys. Keep supporting😉

[@zoom0819]

You have explained so clearly! Please post more such content

[@therisingedge]

Sure, more content on the way!!

[@haricoolty]

Sir ji aap great ho. Apki videos ne pass krwa dia . Thank u sirji 💥

[@therisingedge]

😄😄

[@shreyakumari5350]

I will watch all your videos..Things now appear so simple. Thank you so much !

[@therisingedge]

Happy to hear that!

[@jothis3953]

The explanation is crystal clear in very less amount of time. Waiting for more related videos. Thank you.

[@therisingedge]

Thank you so much Jothi, more videos coming soon.

[@jothis3953]

@@therisingedge waiting to watch

[@himanikumar7979]

Sab samjh aa gya sir. Thank you!

[@therisingedge]

That's great😀

[@nitdawg007]

Thank you for clear and concise explanation.

[@akshitajain9964]

Very creative and informative!

[@shivambhati3388]

Thoroughly explained 😃🙂

[@b80thatiyashwanth53]

Woww thanks a lot..Such a beautiful explaination made such typical topic a piece of cake... ❤️❤️

[@therisingedge]

Glad you liked it!!

[@ashokanbalan]

Good job Yash. Excellent presentation.

[@therisingedge]

Thanks Ashok!!

[@harishannadata8268]

Great presentation. Looking forward for more!!!

[@therisingedge]

Thank you Harish, next video coming soon!!

[@souravgoyal3338]

PERFECT EXPLANATION

[@kollasivaramakrishna6732]

bro this playlist is gold

[@saibhuvan30]

I really loved your way of explanation and Please do more such concepts in VLSI

[@Manikumar-gt9ov]

Wow...great clarity and explanation

[@lorforlinux]

Bhau maza aagaya 😮 flawless animation and very clear explanation. Keep it up yaara 👌

[@suprbhakumari7919]

very clear explaination.....please upload more videos.....they are really helpful

[@therisingedge]

Thank you, I will

[@varsha6330]

Thank You 🙏

[@sanhorizon777]

Wow this really gave me the concept I was looking for.

[@cowbig8342]

Very very clear,a great explain

[@ramanakunduru4726]

😎Nice Explanation Bro.... 🔥

[@therisingedge]

Thank you 🙂

[@nithyashree5327]

Thanks for giving us this explanation❤

[@vikramadithya9597]

Can you please explain concepts on Power related also. Thanks for the video really informative.

[@anishaagarwal9192]

Going great

[@therisingedge]

Thanks😄

[@praneethbogavilli5199]

Good explanation. Waiting for a lot more vidoes

[@therisingedge]

Sure 👍

[@loyal8060]

thank you so much bro, this is the concise explanation.

[@thatguy6442]

I found Gold. Thanks Yash

[@dont_care-x]

thanks for making it easily understandable. Great work

[@bhumikachaudhari5332]

Thanks a lot! Very helpful video.

[@prabhasiva659]

Your concept is good but we all that setup time is checked at capture of the flop and hold is checked at launch edge . can you relative this statement with your concept so that it will bit clear. any way super explanation ....

[@alhasan5017]

Thank you so much

[@therisingedge]

You're most welcome

[@alterguy4327]

Thanks a lot

[@gauravkaushal1037]

Really great video, just a small query, The time that it takes after the positive edge of clock for the input to propagate from node X(where the value was retained) through Y to the slave part and hence the output, is that the clk2Q delay? And can I think of hold time in this way as the time it takes for the negative level sensitive gates to switch off?

[@therisingedge]

Hi Gaurav, thanks for your feedback and the query. Your understanding of the clk2Q delay is correct. And for the hold time, it is partially correct. First of all, the transmission gates are edge sensitive (level sensitive are latches) and I think you meant the gate number 1 that is turning off at the positive edge. Actually the hold time is determined by 2 different delays and this is just one of them. I have talked about them in the next video (STA-3). I hope that after watching that, it will be more clear to you. And still, if any doubt remain, kindly let me know🙂

[@tomoishandsome]

excellent explanation!!

[@tramontz2998]

Very good!

[@ranabasit6046]

Awesome bro...keep it up

[@goldenera1752]

great bhiaya

[@VLSI260]

After d and before q in that's diagram they added extra inverters...what is the use of that ..if we want delay then we can use buffer itself also na

[@aditijain4351]

Very good 👌👌

[@sumiranbhasin1325]

Thank you so much sirji. Please provide some questions too sir

[@therisingedge]

We'll do lot of problems, don't worry.

[@srinivas8030]

You have to add the clock to Q delay in this video for better. understanding

[@palakmishra2867]

Great!!

[@dhruvrana5996]

💯🔥🔥

[@Awakened_Pot]

why are inverters required in internal latches?

[@saravananm92]

I am missing to understand, how metastability comes in here. The video does not explain, possibility of meta-stability. Its note a state of incorrect data, but voltage levels are such that , its nondeterministic. I guess there is a transient characteristics playing a role.

[@RishuKumar016]

Great video and very informative. Can you please make a video on Transmission gates also and in the meanwhile can you share any resource from where I can study it?

[@therisingedge]

Thanks Rishu, will consider your request. And for the resources, I actually use my own notes that I have made while preparing for the placements. I did not followed any particular resource, but looked online for whatever I could find and study everything available until things made sense.

[@srinivas8030]

It was a very nice explanation. but, at 5:18 won't the output from flip flop would be ~X which is not expected from a DFF but with a TFF. please look into this.

[@srinivas8030]

Got clarified there was a, not gate just after the signal was passed.

[@srinivas8030]

I mean X is itself ~D

[@sanyamjain8225]

I have a doubt.. Why are inverters there in internal structure of latch..I mean If we remove all the three inverters..then also it is working as a D-Latch. Please explain

[@alterguy4327]

It took 5 years to understand the topic clearly

[@deepikaapoobalaraja8242]

positive level or edge

[@azhagans5333]

Don't understand why hold time, !!

[@aayushiankan5681]

Omg ... electronics can be cute😅

[@chandumadhumanthi]

background music is so annoying