Shouldnt the t_hold parameter be multiplied by 1.1 because we are trying to stress test it and so a longer t_hold should give a more pessimistic constraint
@VLSIAcademyhub7 ай бұрын
Longer thold is optimistic, it should be lesser since it is minimum constraint
@hardikjain-brb6 ай бұрын
@@VLSIAcademyhub No shorter hold is optimistic since T_hold decreases T_req and so Arrival > Reqd is easily met ; T_hold should be multiplied by 1.1
Please cover set_max_delay constraints and when we can replace set_output_delay with set_max_delay
@amarnathchaurasiya3418 Жыл бұрын
CPP value will be add in RT during setup slack calculation and subtract during hold slack calculation??
@adilkj16069 ай бұрын
You are correct
@redheatredheat99062 жыл бұрын
So what you are effectively saying is that the common path delay in the OCV setup check case, in both the launch(late) and capture(early) cases or path delay value calculations, is the one with the lower(early) derate multiplied? Because that is what the CRPR subtraction is leading to effectively.
@redheatredheat99062 жыл бұрын
@@VLSIAcademyhub Correct and that cell delay value you are choosing with larger derate multiplied for steup and smaller derate value in hold case, this is what I am asking
Should we do CRPR subtraction even for the setup check? Both the launch and capture clocks are not on the same cycle. Capture happens once cycle after the launch.
@srivenibolla14142 жыл бұрын
@@VLSIAcademyhub But in the reports , for setup CRPR is added.. And for hold CRPR is subtracted.. why we are talking like that sir ?
@dinhbuts Жыл бұрын
Is OCV applied only for reg2reg type path or other types (in2reg, reg2out..) If we use both OCV and AOCV methods, does AOCV method overwrite OCV setting?
@Shahidsoc8 ай бұрын
FF2 time need to be pushed for worst case ? but you degraded as pull ?
@VLSIAcademyhub7 ай бұрын
could u please elaborate your question ?
@PRASHANTHKUMAR86819 ай бұрын
While calculating CRPR value for setup, common clock path value has not been multiplied but for hold it is multiplied may I know the reason why ?
@asmamohsin71592 жыл бұрын
If we are adding CPPR in the hold path, shouldn't we subtract this path delay from launch and capture clock path then? like it should be Launch clock path =0.6 * 0.9 Capture clock path = 0.75 * 1.2 CPPR =0.25 (1.2-0.9)
@kishore-px2cc Жыл бұрын
Do we apply derates for library setup and hold time
@kishore-px2cc Жыл бұрын
Why sir ?
@hitanshuvibhute14892 жыл бұрын
how do we solve the hold violation caused by applying derate?
@hramtekkar Жыл бұрын
add delay to datapath ; or reduce skew.
@cskfans1585 Жыл бұрын
why t setup is multiplied with 1.1 shouldn't it be multiplied with 1.2