8. TTL NAND Gate (Totem Pole Output) Analysis in Hindi | TECH GURUKUL By Dinesh Arya

[@iaspawanambati6019]

Excellent sir itna tricky topic ko bahut mast samajhaya apne god bless u sir live long life sir

[@TechGurukul]

Pawan Ambati thanks

[@samir4838]

In class lecture i get totally confused but after seeing this vdo all doubt is clear, thank you sir for this prestigious description

[@dhankthapamagar3389]

Very very Nicely done! I saw other videos where they haven't explained why transistor Q4 is not turning on( using simple logics it seems that Q4 is also ON)

[@deepalidalvi1477]

sir how do you take 0.2 volt 0.65 and sometime 0.7 volt please do explain it ...

[@shubhamkumar8083]

One of the best sir Ise aacha explain nahi ho skta I am just ur faan sir

[@TechGurukul]

Because this is the voltage required to forward bias the base emitter Junction (that is a PN Junction) which is approximately equal to the voltage across depletion layer. You may also refer videos about PN Junction Diode and depletion layer in Semiconductor Diode Playlist for better understanding.

[@aayushisharma4752]

Thank you sir

[@rajkumarmeena3633]

One of the best explanation so far.... Who disliked the video are arts and commerce students... 😂😂

[@yasirarfathfarooqie6290]

Best and easy lecture on ttl in youtube

[@pthe1689]

Thanks sir🙏 ... i had messy notes in my copy so i got confused .... Now everything is clear 👍👍

[@lalchandra4590]

This teacher is gems for all electronics student.

[@Manasvi-dw2od]

@lalchandra4590 even for cse

[@shivamsethi3265]

Sir lecture bahut hi badhiya Tha...thank u Soo much sir

[@harshitsinghbanaswara2003]

👋Sir , Please Explain me Vbe3 pr apne 0.7v liya hai aur kayi bar aap 0.65v lete ho Konsa kab Lena hai please bata do🙏🏻🙏🏻🙏🏻

[@neeltej4123]

hats off to u sir, u r the best !!

[@shruthikalal6866]

It will be helpful if you could explain the truth table of NAND gate using totem pole output.

[@TechGurukul]

Thanks for the concern

[@piyushshukla6934]

Sir please also tell us advantages and application

[@timcook3846]

concept is crystal clear

[@dipanmukhopadhyay2804]

Very well explained sir A large topic was well easily understood .

[@jasminekaur3030]

Beautiful lectures Sir.....Please upload videos on ECL and MOS logic families also

[@Kamal-rn8tj]

Very good explanation, Sir Thank you

[@ryadav9641]

Very very clear explanation 👍.... thank you so much sir

[@smartgamersify]

Sir you're just awesome!🤗🙌🙏 Great explanation

[@oshinkeshwer160]

Great explanation sir

[@ravihandge4468]

Sir please tell us what are the advantages and disadvantages of totem pole output stage.

[@shivamagrahari5425]

VERY WELL EXPLAINED SIR KEEP MAKING THESE VIDEOS

[@subtlechords]

Best explanation... Thanks a lot...

[@ecetech5996]

Plz post the TTL AND gate with pull up resistor

[@ashokgehlot4574]

Ultimate concept sir ji

[@girikgarg1268]

Excellent!

[@AmanKumar-fd8kk]

Best explanation

[@pramodkumarmaurya3253]

Thank you sir for uploaded videos

[@gooddeedmusic108]

amazing. Just amazing explanation about everything, thanks alot sir

[@minakshishukla6546]

Sir.......!! Please provide the video lecture of ECL logic family and MOS and CMOS logic family as soon as possible........ Please sir 🙏🙏🙏🙏

[@mahenderkumarmeena8259]

sir please ye b bataye ki computer senior instructor exam me TTL k objective questions kis type me aaynge , please TTL k objective questions pay viedo banaye , so that hum jese studens ko success mil sake please sir please

[@dhirajactor2401]

Sir high input me ....Vcc t1 ke base ke paas hi q gya ...Vcc t4 ke collector aur base ke paas bhi aa skta h na??

[@Mahashree1014]

sir for writing theory which book is good as per your explanation.

[@TechGurukul]

Modern Digital Electronics by RP Jain

[@Mahashree1014]

@@TechGurukul thank you sir

[@sajimasanthosh473]

Very well explained! Thanks a lot, sir 😊

[@kdkeys12]

Hello sir, what is reason for we need high resistance when T3 transistor is active in Std TTL circuit. kindly explain sir, Regards

[@akashshekhawat5262]

Thank you sir

[@altair6218]

Unbelievable 🙏 I had few doubts in previous lecture which have been cleared now!

[@everything-tothenextlevel2763]

Well done 👍

[@prameelareddy5450]

Sir....is there any disadvantages of this circuit

[@yashwantkumar4998]

you are a great teacher

[@gnyan24]

Sir, if input of multi emitter is low, total current must go outside of that circuit, right. But it is not going, why?

[@hrithiksamala1729]

When the transistor works in the active region it acts as an amplifier, right sir?

[@TechGurukul]

Yes

[@hrithiksamala1729]

@@TechGurukul so far we are dealing with digital ckts but not analog ckts, then what is necessacity of active region of transistor? And also what are the conditions of saying that transistor is in inactive region?

[@AnoNymous-po5sx]

@@hrithiksamala1729 There is no need of considering Active region in digital circuit as we simply need logic 0 or 1. As mentioned earlier, saturated bipolar logic families consider only saturation for ON and cutoff for OFF.

[@35tareenayadav97]

at 15:08 there is mistake ,u wrote vb4 not vbe 3

[@yasirarfathfarooqie6290]

Sir plz plz upload ttl nor gate with totem pole and mos logic families

[@SomitBharadwaj]

Sir fan out of TTL NAND gate ka lecture provide kijiye

[@ankuragarwal4014]

awesome explanation

[@machine-Life]

Nice

[@thespritualindian1331]

Mtlab dhaaga khol Diye Guruji Akdm 👌

[@TechGurukul]

Kya????

[@TechGurukul]

yes definitely Haryanvi Bhai

[@thespritualindian1331]

@@TechGurukul mtlb Sir Great Concept ! Crystal clear Teaching !!

[@thespritualindian1331]

@@TechGurukul Sir one more Request, plzz Continue Analog Electronic Lectures ! I'm going to start this subject tomorrow , so plzz Continue ! It'll be great help for us GATE Aspirants .

[@ZenVerse01]

How do we know that we need 0.9 volt at b point and where did 0.65 came from?

[@mathewsbenny3882]

good explanation

[@TechGurukul]

Thanks

[@abdulkhaliqiqbalsubhani3076]

Where can I get lectures for CMOS

[@aayushisharma4752]

Sir why we are taking voltage across transistor Vbe2 and Vbe3 as 0.65V?

[@ArunKumar-12-i8w]

To turn ON transistor, VBE required is 0.6V to 0.8V, sir has assumed as 0.65V

[@सिंहगौरवरेलवे]

Great sir

[@सिंहगौरवरेलवे]

Please tell me me why clamp diode use

[@AnoNymous-po5sx]

Sir at 15:36, Vb4=Vbe4+Vd+Vce3(sat) kyu nahi hoga? Aap ne sirf Vbe4+Vd likhe hai. Vce3(sat) ko kyu nahi consider kiye?

[@dipalichitroda8205]

Thank you ...😀

[@yasirarfathfarooqie6290]

Thanku sir

[@ghazikhan2624]

Great

[@edusatashrasiddiqui5351]

Great sir..

[@shivamkumarpandey2668]

sir i have doubt on 15.09 should it be Vb3?

[@sushmasharma3601]

How did diode D become forward biased when T2 is in OFF state?

[@TechGurukul]

Sushma Sharma when T2 is off. T3 also in off state and current flows through T4 and diode will be forward bias. Please go through the Lecture, each step is explained.

[@akhilkumarrai5342]

Why collecter current is high in ttl totem pole configuration???

[@user-yo6qn4bq3z]

where is previous lecture?

[@user-yo6qn4bq3z]

where is previous lecture?

[@TechGurukul]

SHIVAANEE SHARMA click on channel name TECH GURUKUL. Then go to Playlist of Digital Logic Families. There you will find the previous Lecture 7

[@abdulikram7248]

👌👌👌👌👌

[@avinashjha4887]

101 combination wala samjha na 😬

[@parasnegi3159]

tameez se baat kr

[@karthikreddy1870]

sir please say in english

[@TechGurukul]

Ok

[@tanishsolanki310]

samaj ni aaraa maaaaaam

[@psychoflame2466]

lol

[@dhankthapamagar3389]

Very very Nicely done! I saw other videos where they haven't explained why transistor Q4 is not turning on( using simple logics it seems that Q4 is also ON)

[@mohitsaini9878]

Thank u sir

[@anjanakundu-j1c]

Amazing explanation

[@mridulkantibaruri32]

THANK YOU SIR

[@GauravGupta-pb8mk]

Thank you sir

[@raunakkumartripathi1892]

great explanation