STA INTERVIEW QUESTION | STA - 6 | Static Timing Analysis | The Rising Edge

Hello,
Welcome to The Rising Edge!
I am Yash and this is the sixth part of Static Timing Analysis.
In this video, you'll see a commonly asked interview problem on STA and learn how to approach it in a very easy manner.
Links to previous parts:
Part 1 (Introduction to Setup/Hold): • INTRODUCTION TO SETUP ...
Part 2 (Reason for Setup/Hold): • WHY SETUP AND HOLD TIM...
Part 3 (Negative Hold Time) : • HOLD TIME CAN BE NEGAT...
Part 4 (Setup Analysis, Max Clk Freq): • SETUP ANALYSIS | MAXIM...
Part 5 (Hod Analysis): • HOLD ANALYSIS | STA - ...
Complete STA Playlist: • Static Timing Analysis
Stay tuned for the complete series, keep learning, and All the Best for your placement preparation.
#STA #interview #StaticTimingAnalysis #Hold #Setup #HoldViolation #SetupViolation #SetupAndHoldTimes #NegativeHold #FlipFlop #DigitalElectronics #PlacementPreparation #Digital #Electronics #placement #Animation
Song: Ikson - Spring (Vlog No Copyright Music)
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Video Link: • Ikson - Spring (Vlog N...

[@aniket_banerjee]

Watched the entire series on STA.....very informative videos with lucid explanations. The video quality and animation is great as well. This is surely a hidden treasure on KZbin. Thank you for the videos!

[@wonder_ash]

Exactly

[@abhinav788]

Combinational logic duplication is really amazing! Its like in real life too... when we think about all the possible cases and keep ourselves prepared... if u think about it!!

[@vaibhavmishra958]

This is an amazing way of explaining frequency optimization techniques and the different pros and cons of doing so. Thank you for the well presented content!

[@praveenmukkiri6374]

Its true Yash, You are fabulous with your clarity and explaination!, Keep it up. All the best

[@therisingedge]

Thank you Praveen😊

[@vomaanvesh939]

U were awesome. Thank you so much for explaining clearly. It's time taking to do these videos its shows your passion and the hard work u put into share ur knowledge. Expecting videos on CDC and Clock dividers.

[@therisingedge]

Thanks Anvesh, will cover those topics soon.

[@jatinkatiyar3991]

What a wonderful explaination, I was searching web for this topic and found this amazing KZbin channel. Thank you!!

[@therisingedge]

Welcome!

[@Priority9842]

Incredible series. Thank you for these great videos. Looking forward to seeing more of them soon!

[@bee.g.s.ashuwin215]

U deserve a round of applause!!!!!!!!!!!

[@therisingedge]

Thanks a lot!

[@bee.g.s.ashuwin215]

It will really help me for my tomorrow's test. Thanks.

[@karthikmg3325]

Amazingly explained understood fully

[@therisingedge]

Thanks a lot Karthik !!

[@vikasbansal4180]

Thank u so much for all these wonderful explainations in very simple way❤👌

[@sushantsinghrajput1602]

Kya baat hai sir 🙌🏼very well explained 👍📝

[@therisingedge]

Thanks SSR !!

[@ghanshu369]

Amazing explanation ! Thanks a lot

[@soukaryabiswas7852]

At 5:14, while calculating the latency, why are we again considering tc2Q as it has been already considered while calculating Tmin & Tmin1?

[@pseudohawk1656]

Bro why did you stop uploading videos? These are really great If possible can you start with analog series also? Thanks

[@sandeshpadiyar9707]

Very clear explanation!.. looking forward to more interesting questions like this😃

[@therisingedge]

Thanks Sandesh, more videos coming!!

[@dbxtra-rb1np]

Thank you very much brother . This helped a lot in short time

[@therisingedge]

Always welcome

[@manojharshavardhan2385]

Good one Yash👍

[@therisingedge]

Thanks Manoj

[@prithvi_krishna]

5:00 The main purpose of increasing frequency is to make the system fast, right ? And here even after increasing the freq, we are getting output, late.

[@shayfux]

note that CL2 delay is irrelevant as the inputs are constant, so even in case of 80nS CL2 (much larger than CL1), the cycle time will remain the same. (of course there are initialization conditions, but I'm assuming they are similar to the non relevant signals in CLs)

[@vipinjain7525]

Well done by

[@nikhil00017]

Thank you for sharing,Very informative. Please make more videos related to this.

[@therisingedge]

Thank you Navin, will upload more videos soon!

[@pgvinaykumar9196]

Great work, keep it up.

[@therisingedge]

Thanks a lot!

[@ankitshaw6737]

Thank u for this amazing content, all the concepts are very well explained.

[@therisingedge]

Glad you like them!

[@sangprisingh2861]

Today is my interview at synopsis 🤞🤞

[@JS-il5zi]

Well explained... thank you it was really helpful.

[@LINZhongyang]

Very nice videos!!! Could you please make more of them?? Very clear explanation

[@sabbirahmed3034]

Thank you for so detailed explanation.

[@kritijaiswal4219]

Thankyou for this informative series. Very well explained!! It has helped me in my Interviews:)

[@therisingedge]

Glad it was helpful!

[@karanamsaiteja]

The videos are incredible. When is the next video coming up?

[@vipinjain7525]

Great work, keep it up👍

[@therisingedge]

Thank you, I will

[@mansiaggarwal4839]

Very informative.. 👍👍

[@therisingedge]

Thanks 🙂

[@sparshnarang1156]

That's really awesome. Would help s lot. 🔥🔥

[@therisingedge]

Best of luck!

[@gauravkaushal1037]

Really great, kindly make more videos on interview problems

[@therisingedge]

Sure Gaurav

[@xkcd000]

Thank you for this series. It was very helpful

[@sunrika7160]

Thankyou sir, some really useful stuff!! 💯✌️

[@therisingedge]

My pleasure!

[@faizanbari4034]

Great explanation.

[@abhishekmanurkar3369]

Beautifully explained the concepts. Keep it up💯

[@sushantsinghrajput1602]

Waiting for the next video

[@extraVaibhav]

Great 👍👍

[@therisingedge]

Thank you 👍

[@digambarbhole9467]

sir, @ 5:52 can we also duplicate combinational logic 1 to get further faster speed ?? can you make video on parallel processing ??

[@pavankalyanlakkireddy4358]

its good for us and we need more videos brother tq

[@tvprakadeesh7914]

We need more videos Yash extraordinary explainition 🔥🔥🔥🔥🔥if you do more videos frequently definitely you will hit more subscribe s

[@therisingedge]

Thank you so much. I'll try to upload more frequently.

[@AbhishekSingh-up4rv]

Can you please make a video on metastable state too ?Your concepts are clear, would love to watch.

[@muralikrishnakorada1749]

Hey, make more videos!! They are really good

[@tharunprathapan5883]

thanks a lot for this series brother, was really helpful. You've earned my sub. Will be really helpful if you further go on to explain more such interview based questions. Thank you

[@gunjanmandape5725]

Thank You so much brother these videos were really helpful

[@kollasivaramakrishna6732]

beautifully explained

[@sparshsharma4508]

Hi Thank you so much for this wonderful content. I had a question about using pipeline flops. Can I insert pipelines to remove hold violations that may occur due to clock skew? Thanks

[@therisingedge]

Yes, you can but you've to make sure that setup is not violated in doing so and overall latency is not of much concern.

[@alokmishra9522]

.

[@ravitejaadusumilli]

more videos please, thankyou :)

[@ngocmanprocoder]

CL1, CL2 can be understood as fetch, decode, execute instruction, right? Thanks you.

[@Sarita.Bijwe21]

Very well Explanation

[@PremKumar-jq3wg]

🙏 please more videos cheyandi sir ☺

[@honeysingh-lu6fq]

This series is so helpful! When can i expect more videos?

[@therisingedge]

Working on more content, will upload soon.

[@anilkumarm6558]

Thank you and good job bro

[@karthikmg3325]

Bro If the hold time does not hold good then we have to change some delays which in turn change clock frequency ?

[@therisingedge]

Yes, there is a tradeoff. If we try to reduce one type of violation more than a certain extent, the other one may get violated. So we've to design the delays in such a manner that it is somewhat midway between both the extremes and no side gets violated.

[@raveenakumari6724]

please upload more videos on digital electronics.

[@ursblogger3410]

Can we introduce positive skew in case the question is only about setup time

[@raghul4044]

upload more videos,it will help in campus placements. thank you

[@raghuram2301]

Please upload more videos on sta

[@divyanshiagarwal8041]

since both the logics accepts only 1bit cant be merge both the logics and create a single logic which gives the desired output?

[@therisingedge]

It can be done, but it is just an example of how such a problem can be tackled. Ultimately, merging or splitting will depend on the specific logic if it is given and the respective delays, such that the desired increase of frequency is achieved without having any violations or significant tradeoffs.

[@bvenkat8140]

how is adding another flipflop regarded as pipelining?

[@divyanshiagarwal8041]

i would like to suggest to remove background music while explanation it will help in better understanding of the concept.

[@therisingedge]

Thanks for the suggestion Divyanshi, will take care of that👍

[@ofek2852]

@@therisingedge In my opinion the music was very nice and it's better than removing it Thank you very much for your videos. They were very comprehensible

[@traveltravelandtravel5294]

Not need to remove music

[@Narennmallya]

The tmux = 1ns was an assumption rite, or in real time circuits tmux is around that range(i.e fast) or is it comparitively slower.. just asking

[@alterguy4327]

Finally

[@vasudeva1906]

cant we bring capture FF before CL2 because as it is a d-ff there will be no loss of functionality. In this case no pipelining or extra circuit is required.

[@Dheeraj4011]

make more videos on retiming and time borrowing

[@rajkumarsah5416]

Bro.. We need more videos

[@pranavgupta4552]

Hi Yash, The videos are amazing and easily understandable. Could you please share the ppt for ckt diagrams u have used ?

[@PremKumar-jq3wg]

Do series of videos on FPGA and Memories

[@akki0133]

Hello bhaia i have saw your detail you are passput from NSIT DELHI how was the college according to MTECH VLSI, HOW IS PLACEMENT, please tell me

[@lokeshTarala]

Can we optimize it more by adding a mux to CL1 just like CL2?

[@maniratnam2653]

You can add mux for CL1 where u can save 2ns because tc2q is 3ns and mux have 1ns In parallel CL1 start transmitting 0 and 1 and take 8ns. 8ns-3ns = 5ns which means output data available after 3ns still it take 5ns to get output from mux and delay of mux is 1ns that will add up 5ns + 1ns = 6ns So we can save 2ns in total.

[@sanyamjain8225]

We need more videos soon

[@PremKumar-jq3wg]

please make more videos, please

[@ngocmanprocoder]

Tmin = Data Arrival Time + Tsu, Data Arrival Time included Tc2q, why do you add it one time in pipeling drawback : Tmin + Tc2q. Thanks a million.

[@no_one8143]

latch based problem plz

[@praveenareddy1524]

My aim is to get job in core electronic companies. Please help me

[@stancex404]

SOMETHING IS WRONG. IN NPTEL DIGITAL IC DESIGN and Neil Weste book, Tskew polarity is opposite.