HOLD TIME CAN BE NEGATIVE!!! | STA-3 | Static Timing Analysis

[@sailajapeddakotla8248]

You know how many pauses that i've to take to get the whole thing completely into my brain but its totally worth investing time in this playlist...🤩

[@saradarandomworld6926]

woowwwww just wow , what a beautiful explanation , best explanation , actually for this topic very less ,lengthy and bearing videos are available in youtube . you just made it simple and detailed it in a small video , thank you bro

[@anjaliagrawal4269]

I was asked regarding Negative Hold time in my interview. You have provided a good explanation of the topic. Thank you 😁

[@therisingedge]

Yeah, it is asked frequently🙂

[@uk4725]

Ayinu?

[@ghanshu369]

Beautifully explained , Thanks a lot !

[@shreyakumari5350]

It will help students a lot!! Very nice job!

[@therisingedge]

Thanks Shreya!!

[@velugubantlapriyanka5854]

In case 3 where you considered Tin as 7ns which means the setup time is increased by +7ns and data should arrive at D pin 7ns+extra setup time prior for it to be captured correctly so definetely negative hold times impose a threat to setup timing making it hard to fix

[@hanu5090]

Yes true Let hold time is decreased by 5ns same amount of time increased in set-up time

[@mansiaggarwal4839]

kya baat hai ladke...kya baat..

[@therisingedge]

😄

[@gauravkaushal1037]

great video, now because of the Tin delay will the setup time also increase by 7ns? Since now an additional 7ns is also needed for the data to reach the first gate. so if before it was 1ns then will it now be 8ns?

[@therisingedge]

Yes, correct, that's why we don't focus on correcting either one of them (Setup or hold) we have to optimize the values such both times are satisfied.

[@prabhasiva659]

When there setup time is negative the will be effected or not can please tell?

[@pavan_pelleti]

🙏🙏🙏 The best...your clarity and quality is SUPERB....but i request you to do more playlists regarding digital electronics,verilog,vlsi

[@nagendraprasad2890]

fixing the hold violation then followed by setup violations would probably ensure that they are fixed for both ends

[@dhamusundaravadivelu5698]

good explanation. i am not sure if there is already a comment about this and please correct me if i am wrong, theoritically library setup time of a flop cell can also be negative, if the datapath delay < clock path delay in the internal structure of the flop.

[@anishaagarwal9192]

Quality content.💯

[@therisingedge]

Thanks, Anisha!!

[@prashantsharma3134]

Hi Yash, thanks for the explanation. In case 3, where hold time is negative, then what will be the setup time for flip flop? will it be any time b/w 0 to 5 nsec.

[@therisingedge]

Hi Prashant, thanks for asking this doubt! No, the setup time will not be in 0-5ns, rather it will be calculated by adding the delays of all the 3 inverters that are there in the path from D to X. So, if the hold time keeps on going in the negative direction, it will cause large setup time constraint, making it difficult to achieve the desired performance(frequency).

[@AbhishekSingh-up4rv]

@@therisingedge Nice ty

[@merebaap8166]

@@AbhishekSingh-up4rv 🐍🐍

[@madhurikam9331]

@@therisingedge what about the transmission gate delay in D to X path while calculating setup time?

[@supriyakaku1725]

What is datapath and colck path

[@akshitajain9964]

Well explained

[@shivambhati3388]

Going Good Sir..

[@uday7777777]

Nice explanation. Thank you very much 👍

[@sattwikghatak9704]

brilliant video presentation and editing as well as explanation, very rarely seen content quality

[@chaitanyab26]

Setup time is not always positive , it can also be negative

[@abish83]

I was about to say the same. But both cant be negative, sum of setup and hold has to be positive.

[@rupamandal3751]

the explanation was awesome, good job :-))

[@therisingedge]

Glad you liked it!

[@IITMIAN_ABHILASH]

Great video

[@therisingedge]

Thanks!

[@shubhangisingh2608]

Why is setup not affecting during negative hold?

[@smartravi271292]

Set up time are considered in two edges, launch and capture but hold only consider in launch edge

[@shikhadas9466]

Do we try to keep the hold time negative while designing?

[@therisingedge]

Hi Shikha, thanks for the query! See, for a Pure flop(containing no extra gates) setup and hold time always will be a positive number. Now, A flop can be a part of a bigger component. Hold Time of a flip flop is a constraint on data path delay so that it remains stable for some time after active clock edge. Higher the value of hold time a flip flop, more strict will be this constraint because data has to remain stable for this much time. So, if you have zero or negative hold time then there is no such constraint on data and hence it helps in meeting hold violations. However, flip flops with negative hold time have a large setup time constraint, making it difficult to achieve the desired performance(frequency). Hence, while designing, we aim to design in such a way that there are no timing violations(setup or hold) while ensuring optimum performance.

[@shikhadas9466]

@@therisingedge Thank you for answering. I have another question. If I have to design a circuit to work on 1GHz and I have a combinational delay of 2ns between two flip-flops then is it possible to make it work on the given frequency? I could add another flop in between but it would add to the area and cost if I had to do this for all flip-flop pairs. Do you have any idea about this?

[@therisingedge]

Assuming that you are working with ideal flops (Zero setup/Hold, c2q), then the only way to make it work on 1GHz is to include delay in the clock path, as we'll have to increase the data required time by at least the combinational delay value of 2ns.

[@RishabhSingh-nh3ow]

Well explained , thank you sir

[@therisingedge]

Glad you liked it

[@sreekantasai1675]

Delay of Transmission gate Tg=5ns doesnt mean it will be turned off after 5ns. It will turn off based on clk whether clk is pos or negitive. Delay Tg=5ns means o/p will be delayed version of i/p by 5ns

[@NAGENDRAARASANK-i2x]

My doubt is if the there are more delays it is only additive in nature right? So, I can't understand this concept...

[@rohanyadala9096]

Super...

[@ananthimanokaran6966]

Hi yash, in case 2 what if the data change happening before the clock that is -2ns .data changes will happen before gate turn off right?

[@ananthimanokaran6966]

And in case 1 data changing reflect on 2ns after clock edge means hold time will be voilated right?

[@Abhishek.B.N]

Hi can you send me the lecture notes

[@himanikumar7979]

Very good video

[@therisingedge]

Thanks, Himani!!

[@RishabhSingh-nh3ow]

Kya chal rha hai ye yahan

[@vibhagoel8889]

👍👍

[@neeleshranjan7827]

i have not got why the setup time is not violated when the hold time is negative. please someone explain it to me.

[@faneeshbansal]

Same with me, if u understood it now, can u pls explain it to me?

[@ravichandranavalgund2679]

If you increase the combo delay setup time also going to increase(in this video he mention doesn’t affect setup which is wrong I guess) but it doesn’t set up time not violate why Bcz any changes to the signal at input prior to clocking needs to go through the delay (combo) so it treated as -ve

[@arunakumari1436]

In 1st case y did u take 5-3 not 5-2

[@shivakumarcheruku1546]

🙏

[@kundankumar-ll8in]

Setup time can also be negative...

[@surendrayerragorla2028]

Why is your voice like this?

[@ashuverma4716]

Can't u explain all this things in hindi,if possible,it would be more clear and more understandable

[@therisingedge]

Will try to, thanks for the suggestion !!

[@inuyashayagami2281]

Dude! Not a good example of latches you have taken in your explnations. :( There were supposed to be Q and Qbar.